SDI released PRB0400 bridge chip, and Wellcore Microelectronics led the domestic substitution of high-end chip
Time:2022-10-16
Views:1580
Source: Huaqiang Electronic Network Author: Well Core Microenterprise
Looking at the global semiconductor market, driven by the geographical governance and innovation wave, China‘s local semiconductor industry is developing vigorously, among which the chip design industry is the first to enter the deep-water area of domestic substitution with its strongest technological leadership. The changes in market demand, technological innovation and changes, and the unpredictable international pattern have all put forward higher requirements for the technological, financial and talent capabilities of chip design enterprises. Among them, the industrial players who braved the deep substitution and blew the attack horn to the high-end chip field need more courage and perseverance.
Recently, Wellcore Microelectronics Technology (Tianjin) Co., Ltd. (hereinafter referred to as "Wellcore Microelectronics" or "Wellcore Microelectronics"), which focuses on developing and leading innovative products, launched a new domestic alternative product - PRB0400 PCIe to SRIO bridge chip (hereinafter referred to as "Wellcore PRB0400") to the market after releasing the 240G network DPU chip SDI2820. Wellcore PRB0400 is a high-performance data transmission bridge chip that is compatible with PCIe Gen2 and RapidIO Gen2 protocols. It is mainly used to meet the interconnection requirements between various components in the highly reliable and low latency computing and processing system, and realize the data interconnection between PCIe protocol network and RapidIO protocol network. This chip can easily realize the seamless connection between SRIO (Serial RapidIO) system and PCIe system, and achieve the integration of the two ecosystems.
Wellcore PRB0400 supports efficient data communication from chip to chip and from board to board. It can be used to connect CPU, DSP, FPGA and other intensive electronic systems. It is used to solve the connection problem between PCIe network and RapidIO network. At the same time, it is embedded with DMA engine and message passing engine, which can achieve efficient transmission of large amounts of data without weak participation of the main control processor. As a PCIe to SRIO bridge chip, Wellcore PRB0400 is widely used in point-to-point interconnection between various processors, or RapidIO data interaction between processors and other functional realization scenarios. It has a huge market space in base station transmission, distributed computing, image processing and other application fields.
Deeply tap into the unique needs of local customers and create 25 enhanced functions
Fig. 1 Structure of Well Core PRB0400 Chip
Well core PRB0400 adopts full forward research and development, and has five main functions: PCIe interface, S-RIO interface, message engine, mapping engine and block DMA engine. At the initial stage of product definition, we conducted detailed and rigorous market research, widely absorbed the application suggestions of many domestic customers in the development process, and developed additional functions according to customer needs. On the premise of being compatible with all the functions of the benchmarking device and not affecting the official drive, compared with the relevant products of international manufacturers, the well core PRB0400 has added 7 business related items, 6 adaptation related items, 5 maintainability related items, and 7 robustness related items, a total of 25 function enhancements, which can better meet the application needs of local customers. At the same time, the core micro R&D team has accumulated profound experience in use and positioning, and can provide better local support services to local customers.
In well core PRB0400 chip, PCIe interface is responsible for all physical layer, data link layer and transport layer protocols related to PCIe, and S-RIO interface is responsible for all physical layer and transport layer protocols related to S-RIO. The message engine is used for RapidIO logic layer message transmission, and both the receiving and sending channels support eight independent processing engines. The mapping engine is used for mapping and conversion between PCIe and RapidIO, which can be split and reorganized as needed. The block DMA engine supports eight independent DMA channels, and each DMA channel can perform read or write operations according to the descriptor.
In terms of system design, well core PRB0400 can replace benchmarking international products in situ and is compatible with its official drive. In addition, well core PRB0400 is compatible with domestic mainstream CPU and DSP, and has completed the corresponding ecological test. At present, the ecological tests corresponding to PCIe RC equipment such as Feiteng, Longxin, x86 and Zynq have been completed, and the original replacement of hardware and software of related products from international manufacturers has been realized.
Aim at multiple application scenarios and open a new infrastructure market of 4 billion yuan
RapidIO protocol is the global mainstream international standard for embedded system interconnection (ISO/IEC18372), and PCIe is a high-speed serial computer expansion bus standard. Both protocols are widely used in China‘s information infrastructure, especially in device level, board level and system level devices, where PCIe protocol and RapidIO protocol are widely used. As a PCIe to RapidIO protocol chip, the well core PRB0400 has a broad market space in the typical application scenario of new infrastructure construction facilities. For example, in order to ensure real-time performance in communication base stations, high-speed real-time transmission bus RapidIO protocol and PCIe protocol are generally used. In the maintenance management system of RapidIO network, RapidIO switching chip and PCIe to SRIO bridge chip are used for point-to-point interconnection between various processors or RapidIO data interaction and other functions. For the processor and RapidIO network connection system, the PCIe to RapidIO bridge chip is used to solve the system application problems and improve the system‘s computing efficiency.
In video and image applications, system designers need to use a large number of DSP or FPGA to perform encoding/decoding/transcoding, or FFT (Fast Fourier Transform) on large data arrays. RapidIO protocol is most suitable for this DSP/FPGA cluster. However, the analog front-end of the system is usually a sensor, and the stream data is terminated in FPGA (such as the camera subsystem). This is usually in a PCIe network with a PC back end. In these applications, well core PRB0400 can help designers build a bridge between PCIe network and RapidIO DSP/FPGA cluster.
In wireless base stations, RapidIO is the interconnection technology used by baseband processing cards of LTE, WCDMA and TD-SCDMA. RapidIO connects a group of DSP, processor and FPGA clusters locally on the baseband processor for MAC and PHY layer processing. However, the LTE standard improves the performance of existing RapidIO microprocessors. Wellcore PRB0400 provides wireless equipment manufacturers with an additional option to use x86 processors with excellent MIPs in baseband cards dominated by RapidIO. In these board designs, RapidIO is the interconnection bus between devices and used for backplane interconnection. The x86 processor can now be used with other RapidIO devices on the baseband card, and it is applied in the point-to-point multiprocessor network with the message performance of RapidIO.
In high-performance processing applications, Wellcore PRB0400 supports the use of PCIe processors for RapidIO backplanes, providing system designers with the best of both worlds - the floating point and MIPs processing capabilities of the latest generation of X86 solutions, and the excellent point-to-point network performance of RapidIO architecture. By combining the well core PRB0400 with the well core micro switch chip, the payload processor card with the X86 processor can be used with the existing RapidIO 1.3 backplane working at up to 3.125 Gbaud, or the same card can be used with the RapidIO Gen2 compatible backplane working at 5 Gbaud.
The wave of domestic new infrastructure industry, the construction of the East Digital West Computing Project and the rise of local server chip manufacturers have made the demand for domestic bridge chips very strong. For example, in communication base stations, distributed computer systems, video conferencing, image processing systems and other scenarios, with the improvement of user needs and sense of experience, the requirements for basic data processing in various fields are more stringent, resulting in increasing complexity of processing algorithms and increasing data transmission. According to the person in charge of Well Core Micro, it was found in the early market research that the domestic market is in urgent need of PCIe to RapidIO protocol chips, and the overall market capacity is expected to exceed 4 billion yuan in the future. In addition, during the development of well core PRB0400, it has been widely concerned by domestic mainstream CPU manufacturers and given high priority technical support. It is understood that well core PRB0400 has started to send samples to customers, and will achieve mass production and supply by the end of this year.
Deeply cultivate SDI interconnection technology, and well core micro leads high-end chip localization
In the past five to ten years, the local semiconductor industry has achieved rapid growth, especially the chip design industry, which has achieved a wide range of domestic substitution in analog chips and digital chips. However, today, import substitution has entered the deep-water area, especially the deep-water substitution of high-end chips. Enterprises need to shoulder the heavy task of gnawing the hard bone and challenge the "deep-water area" and even the "no man‘s land". Interconnection technology is one of the problems that need to be overcome, while the traditional interconnection chip technology is still monopolized by foreign giants.
As a new direction of interconnection technology, Software Defined Interconnection (SDI) technology was proposed by Academician Wu Jiangxing of the Chinese Academy of Engineering in 2009. Its core is to break the rigid architecture of the existing network and achieve a network system of full dimensional software definition from the physical layer, data link layer, network layer to the business layer, so as to change the rigid network into a flexible network and build a definable, reconfigurable Reconfigurable software definition architecture. SDI technology can provide efficient flat and flexibly defined interconnection for new data centers, cloud computing and other information infrastructures, provide on-demand "flexible bones" for automated driving, instant confidential communication and other situational network dynamic services, and provide flexibly defined "on-demand connections" for the swarm intelligence of large-scale sensor nodes in the Internet of Things era.
The core technology team of Wellcore Micro, which regards "core making for the next generation network" as its enterprise mission, has fully participated in the whole process of SDI from concept to chip realization, and has enabled new infrastructure by establishing SDI alliance and developing chip based SDI technology. The founding team of Wellcore Micro Core not only has a deep accumulation in SDI technology, but also has rich experience in chip development. At present, Wellcore Micro has obtained 80 invention patents and 168 patents. It has successfully developed RapidIO switching chip - Wellcore NRS1800, software definition interconnection switching chip - Wellcore SDI3210, endogenous security switching chip - Wellcore ESW5610, PCIe to SRIO bridge chip - Wellcore PRB0400, 240G intelligent network card chip - Wellcore SDI2820 and other domestic leading chip products. More than 10 chips are under research for the construction of 5G base stations New infrastructure construction facilities such as big data center construction provide core technical support.
Protocol conversion chip is an important branch of SDI technology. The release of PCIe to RapidIO bridge chip Wellcore PRB0400 will serve as an important link in the "end-to-end new SDI environment" layout of Wellcore Microelectronics, and support the market space of Wellcore Microdrivers in the order of 100 billion yuan. As the leader of SDI technology, Wellcore Microenterprise has gradually become known for its technical advantages and market recognition by continuously expanding its product roadmap based on SDI technology. It is understood that in 2021, the sales of Well Core Micro increased by more than 300% year on year, the number of industrial customers has expanded to more than 300, and the first round of financing of 50 million yuan was completed in March 2022.
On the basis of deep layout of SDI technology, Wellcore Micro will explore the technology and industrial road of "SDI approaches neural networks, and neural networks drive intelligence" in the medium and long term in the future. Through SDI "neural networks", it will integrate various types of "neurons" such as CPU, GPU, IPU, NPU, TPU, DSP, and work together to build a green and safe intelligent world.
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