How does PCB layered stacking control EMI?
Time:2022-04-15
Views:2145
There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coating, selecting appropriate EMI suppression parts, EMI simulation design and so on. Starting from the most basic PCB layout, this paper discusses the function and design skills of PCB layered stacking in controlling EMI radiation.
As far as the IC on our circuit board is concerned, the power layer around the IC can be regarded as an excellent high-frequency capacitor, which can collect the part of energy leaked by the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of the excellent power supply layer is small, so the transient signal synthesized by the inductance is also small, so as to reduce the common mode EMI. Of course, the connection from the power layer to the IC power pin must be as short as possible, because the rising edge of the digital signal is faster and faster. It is better to connect directly to the pad where the IC power pin is located, which will be discussed separately. In order to control common mode EMI, the power supply layer should help decoupling and have low enough inductance. This power supply layer must be a pair of well-designed power supply layers. One might ask, how good is good? The answer to the question depends on the layering of the power supply, the material between the layers and the operating frequency (i.e. a function of IC rise time). Generally, if the spacing of power layers is 6mil and the interlayer is FR4 material, the equivalent capacitance per square inch of power layer is about 75pF.
Obviously, the smaller the layer spacing, the greater the capacitance. There are not many devices with a rise time of 100 to 300ps, but according to the current development speed of IC, devices with a rise time of 100 to 300ps will account for a high proportion. For circuits with 100 to 300ps rise time, 3mil layer spacing will no longer be suitable for most applications. At that time, it is necessary to adopt the delamination technology with layer spacing less than 1mil and replace FR4 dielectric material with material with high dielectric constant. Now, ceramics and ceramic plastics can meet the design requirements of 100 to 300ps rise time circuits. Although new materials and methods may be used in the future, for the common 1 to 3ns rise time circuits, 3 to 6mil layer spacing and FR4 dielectric materials today, it is usually enough to deal with high-end harmonics and make the transient signal low enough, that is, the common mode EMI can be reduced very low. The example of PCB layered stacking design given in this paper will assume that the layer spacing is 3 to 6mil.
From the perspective of signal routing, a good layering strategy should be to place all signal routing on one or several layers, which are close to the power layer or grounding layer. For power supply, a good layering strategy should be that the power supply layer is adjacent to the grounding layer, and the distance between the power supply layer and the grounding layer should be as small as possible. This is what we call "layering" strategy.
PCB stacking what kind of stacking strategy helps to shield and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer, and single voltage or multiple voltages are distributed in different parts of the same layer. The case of multiple power layers will be discussed later.
power bus
Properly placing a capacitor of appropriate capacity near the power supply pin of the IC can make the jump of IC output voltage faster. However, the problem does not stop there. Due to the limited frequency response of the capacitor, it is impossible for the capacitor to generate the harmonic power required to drive the IC output cleanly in the full frequency band. In addition, the transient voltage formed on the power bus will form a voltage drop at both ends of the inductance of the decoupling path. These transient voltages are the main common mode EMI interference source. How should we solve these problems?
As far as the IC on our circuit board is concerned, the power layer around the IC can be regarded as an excellent high-frequency capacitor, which can collect the part of energy leaked by the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of the excellent power supply layer is small, so the transient signal synthesized by the inductance is also small, so as to reduce the common mode EMI. Of course, the connection from the power layer to the IC power pin must be as short as possible, because the rising edge of the digital signal is faster and faster. It is better to connect directly to the pad where the IC power pin is located, which will be discussed separately. In order to control common mode EMI, the power supply layer should help decoupling and have low enough inductance. This power supply layer must be a pair of well-designed power supply layers. One might ask, how good is good? The answer to the question depends on the layering of the power supply, the material between the layers and the operating frequency (i.e. a function of IC rise time). Generally, if the spacing of power layers is 6mil and the interlayer is FR4 material, the equivalent capacitance per square inch of power layer is about 75pF.
From the perspective of signal routing, a good layering strategy should be to place all signal routing on one or several layers, which are close to the power layer or grounding layer. For power supply, a good layering strategy should be that the power supply layer is adjacent to the grounding layer, and the distance between the power supply layer and the grounding layer should be as small as possible. This is what we call "layering" strategy.
PCB stacking what kind of stacking strategy helps to shield and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer, and single voltage or multiple voltages are distributed in different parts of the same layer. The case of multiple power layers will be discussed later.
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There are some potential problems in the design of 4-ply board. Firstly, for the traditional four layer board with a thickness of 62mil, even if the signal layer is in the outer layer and the power supply and grounding layer are in the inner layer, the spacing between the power supply layer and the grounding layer is still too large.
If the cost requirement is the first, the following two alternatives to the traditional 4-ply board can be considered. Both schemes can improve the performance of EMI suppression, but they are only suitable for occasions where the density of components on the board is low enough and there is enough area around the components (place the required power copper coating). The first is the preferred scheme. The outer layer of PCB is stratum, and the middle two layers are signal / power layer. The power supply on the signal layer is routed with a wide line, which can make the path impedance of the power supply current low and the impedance of the signal microstrip path low. From the perspective of EMI control, this is the best existing 4-layer PCB structure. The outer layer of the second scheme goes through the power supply and ground, and the middle two layers go through the signal. Compared with the traditional 4-layer board, the improvement of this scheme is smaller, and the interlayer impedance is as poor as the traditional 4-layer board. If you want to control the routing impedance, the above stacking schemes should be very careful to arrange the routing under the power supply and grounding copper island. In addition, the copper laying islands on the power supply or stratum should be interconnected as much as possible to ensure the connectivity between DC and low frequency.
6-layer plate
If the component density on the 4-layer board is relatively large, it is better to use the 6-layer board. However, some lamination schemes in 6-layer board design do not have good shielding effect on electromagnetic field, and have little effect on reducing the transient signal of power bus. Two examples are discussed below.
In the first example, the power supply and ground are placed on the second and fifth layers respectively. Due to the high copper clad impedance of the power supply, it is very unfavorable to control the common mode EMI radiation. However, from the point of view of signal impedance control, this method is very correct. In the second example, the power supply and ground are placed on the third and fourth layers respectively. This design solves the problem of copper clad impedance of the power supply. Due to the poor electromagnetic shielding performance of the first and sixth layers, the differential mode EMI increases. If the number of signal lines on the two outer layers is the least and the routing length is very short (less than 1 / 20 of the highest harmonic wavelength of the signal), this design can solve the problem of differential mode EMI. The non component and non wiring areas on the outer layer are filled with copper and the copper clad area is grounded (every 1 / 20 wavelength is an interval), which is particularly good for the suppression of differential mode EMI. As mentioned earlier, the copper laying area shall be connected with the internal grounding layer at multiple points. The general high-performance 6-layer board design generally distributes the 1st and 6th layers as the stratum, and the 3rd and 4th layers are powered and grounded. Because there are two intermediate double microstrip signal line layers between the power supply layer and the ground layer, the EMI suppression ability is excellent. The disadvantage of this design is that the routing layer has only two layers. As mentioned earlier, if the outer wiring is short and copper is laid in the non wiring area, the same stacking can be achieved with traditional 6-layer plates. Another 6-layer board layout is signal, ground, signal, power supply, ground and signal, which can realize the environment required for advanced signal integrity design. The signal layer is adjacent to the grounding layer, and the power layer is paired with the grounding layer. Obviously, the disadvantage is the unbalanced stacking of layers. This usually brings trouble to processing and manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. After copper filling, if the copper coating density of the third layer is close to the power layer or grounding layer, this board can not be strictly regarded as a circuit board with balanced structure. The copper filling area must be connected to power supply or grounding. The distance between the connecting vias is still 1 / 20 of the wavelength. It is not necessary to connect everywhere, but it should be connected ideally.
Because the insulation isolation layer between multi-layer boards is very thin, the impedance between layers of 10 or 12 layer circuit boards is very low. As long as there is no problem with layering and stacking, excellent signal integrity can be expected. There are many difficulties in processing and manufacturing 12 ply plates according to the thickness of 62mil, and there are not many manufacturers who can process 12 ply plates.
Because there is always an insulating layer between the signal layer and the loop layer, the scheme of allocating the middle 6 layers to route the signal line in the 10 layer board design is not the best. In addition, it is important to make the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power supply, ground, signal, signal, ground and signal. This design provides a good path for signal current and its loop current. The appropriate routing strategy is that the first layer is routed along the X direction, the third layer is routed along the Y direction, the fourth layer is routed along the X direction, and so on. Visually look at the routing. Layers 1 and 3 of layer 1 are a pair of layered combinations, layers 4 and 7 are a pair of layered combinations, and layers 8 and 10 are the last pair of layered combinations. When the routing direction needs to be changed, The signal line on the first layer shall be "Vias" change direction after reaching layer 3. In fact, this may not always be done, but as a design concept, it should be followed as much as possible. Similarly, when the routing direction of the signal changes, it should be from layer 8 and layer 10 or from layer 4 to layer 7 through vias. This wiring can ensure the tightest coupling between the forward path of the signal and the loop. For example, if the signal is routed on layer 1, the loop is on layer 2 and only on layer 2 Line, Even if the signal on the first layer is transferred to the third layer through the "via", its circuit is still in the second layer, so as to maintain the characteristics of low inductance, large capacitance and good electromagnetic shielding performance. What if the actual wiring is not like this? For example, the signal line on the first layer passes through the via to the tenth layer, at this time, the circuit signal has to find the grounding plane from the ninth layer, and the circuit current should find the nearest grounding via (such as the grounding pin of elements such as resistance or capacitance). If you happen to have such a via nearby, you‘re really lucky. If there is no such close via available, the inductance will increase, the capacitance will decrease, and the EMI will increase. When the signal line must leave the current pair of wiring layers to other wiring layers through vias, grounding vias should be placed near the vias, so that the loop signal can return to the appropriate grounding layer smoothly. For the layered combination of layer 4 and layer 7, the signal loop will return from the power layer or ground layer (i.e. layer 5 or layer 6), because the capacitive coupling between the power layer and ground layer is good and the signal is easy to transmit.
Design of multi power layer
If two power layers of the same voltage source need to output large current, the circuit board shall be arranged into two groups of power layers and grounding layers. In this case, an insulating layer is placed between each pair of power layers and the grounding layer. In this way, we can get two pairs of power busbars with equal impedance. If the stack of power layers causes unequal impedance, the shunt will be uneven, the transient voltage will be much larger, and the EMI will increase sharply.
If there are multiple power supply voltages with different values on the circuit board, multiple power supply layers are required accordingly. Remember to create their own paired power supply layers and grounding layers for different power supplies. In the above two cases, when determining the position of the paired power layer and ground layer on the circuit board, remember the manufacturer‘s requirements for the balance structure.
In conclusion, since most of the circuit boards designed by engineers are traditional printed circuit boards with a thickness of 62mil and without blind holes or buried holes, the discussion of circuit board layering and stacking in this paper is limited to this. For circuit boards with too large thickness difference, the layering scheme recommended in this paper may not be ideal. In addition, the processing process of circuit boards with blind holes or buried holes is different, and the layering method in this paper is not applicable.
In the circuit board design, the thickness, via process and the number of layers of the circuit board are not the key to solve the problem. Excellent layered stacking is the key to ensure the bypass and decoupling of the power bus, minimize the transient voltage on the power layer or grounding layer, and shield the signal and the electromagnetic field of the power supply. Ideally, there should be an insulating isolation layer between the signal wiring layer and its circuit grounding layer, and the smaller the paired layer spacing (or more than one pair) should be, the better. According to these basic concepts and principles, we can design a circuit board that can always meet the design requirements. Now, the rise time of IC has been very short and will be shorter. The technology discussed in this paper is essential to solve the problem of EMI shielding.
4-layer plate
There are some potential problems in the design of 4-ply board. Firstly, for the traditional four layer board with a thickness of 62mil, even if the signal layer is in the outer layer and the power supply and grounding layer are in the inner layer, the spacing between the power supply layer and the grounding layer is still too large.
If the cost requirement is the first, the following two alternatives to the traditional 4-ply board can be considered. Both schemes can improve the performance of EMI suppression, but they are only suitable for occasions where the density of components on the board is low enough and there is enough area around the components (place the required power copper coating). The first is the preferred scheme. The outer layer of PCB is stratum, and the middle two layers are signal / power layer. The power supply on the signal layer is routed with a wide line, which can make the path impedance of the power supply current low and the impedance of the signal microstrip path low. From the perspective of EMI control, this is the best existing 4-layer PCB structure. The outer layer of the second scheme goes through the power supply and ground, and the middle two layers go through the signal. Compared with the traditional 4-layer board, the improvement of this scheme is smaller, and the interlayer impedance is as poor as the traditional 4-layer board. If you want to control the routing impedance, the above stacking schemes should be very careful to arrange the routing under the power supply and grounding copper island. In addition, the copper laying islands on the power supply or stratum should be interconnected as much as possible to ensure the connectivity between DC and low frequency.
6-layer plate
In the first example, the power supply and ground are placed on the second and fifth layers respectively. Due to the high copper clad impedance of the power supply, it is very unfavorable to control the common mode EMI radiation. However, from the point of view of signal impedance control, this method is very correct. In the second example, the power supply and ground are placed on the third and fourth layers respectively. This design solves the problem of copper clad impedance of the power supply. Due to the poor electromagnetic shielding performance of the first and sixth layers, the differential mode EMI increases. If the number of signal lines on the two outer layers is the least and the routing length is very short (less than 1 / 20 of the highest harmonic wavelength of the signal), this design can solve the problem of differential mode EMI. The non component and non wiring areas on the outer layer are filled with copper and the copper clad area is grounded (every 1 / 20 wavelength is an interval), which is particularly good for the suppression of differential mode EMI. As mentioned earlier, the copper laying area shall be connected with the internal grounding layer at multiple points. The general high-performance 6-layer board design generally distributes the 1st and 6th layers as the stratum, and the 3rd and 4th layers are powered and grounded. Because there are two intermediate double microstrip signal line layers between the power supply layer and the ground layer, the EMI suppression ability is excellent. The disadvantage of this design is that the routing layer has only two layers. As mentioned earlier, if the outer wiring is short and copper is laid in the non wiring area, the same stacking can be achieved with traditional 6-layer plates. Another 6-layer board layout is signal, ground, signal, power supply, ground and signal, which can realize the environment required for advanced signal integrity design. The signal layer is adjacent to the grounding layer, and the power layer is paired with the grounding layer. Obviously, the disadvantage is the unbalanced stacking of layers. This usually brings trouble to processing and manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. After copper filling, if the copper coating density of the third layer is close to the power layer or grounding layer, this board can not be strictly regarded as a circuit board with balanced structure. The copper filling area must be connected to power supply or grounding. The distance between the connecting vias is still 1 / 20 of the wavelength. It is not necessary to connect everywhere, but it should be connected ideally.
10 ply board
Because the insulation isolation layer between multi-layer boards is very thin, the impedance between layers of 10 or 12 layer circuit boards is very low. As long as there is no problem with layering and stacking, excellent signal integrity can be expected. There are many difficulties in processing and manufacturing 12 ply plates according to the thickness of 62mil, and there are not many manufacturers who can process 12 ply plates.
Because there is always an insulating layer between the signal layer and the loop layer, the scheme of allocating the middle 6 layers to route the signal line in the 10 layer board design is not the best. In addition, it is important to make the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power supply, ground, signal, signal, ground and signal. This design provides a good path for signal current and its loop current. The appropriate routing strategy is that the first layer is routed along the X direction, the third layer is routed along the Y direction, the fourth layer is routed along the X direction, and so on. Visually look at the routing. Layers 1 and 3 of layer 1 are a pair of layered combinations, layers 4 and 7 are a pair of layered combinations, and layers 8 and 10 are the last pair of layered combinations. When the routing direction needs to be changed, The signal line on the first layer shall be "Vias" change direction after reaching layer 3. In fact, this may not always be done, but as a design concept, it should be followed as much as possible. Similarly, when the routing direction of the signal changes, it should be from layer 8 and layer 10 or from layer 4 to layer 7 through vias. This wiring can ensure the tightest coupling between the forward path of the signal and the loop. For example, if the signal is routed on layer 1, the loop is on layer 2 and only on layer 2 Line, Even if the signal on the first layer is transferred to the third layer through the "via", its circuit is still in the second layer, so as to maintain the characteristics of low inductance, large capacitance and good electromagnetic shielding performance. What if the actual wiring is not like this? For example, the signal line on the first layer passes through the via to the tenth layer, at this time, the circuit signal has to find the grounding plane from the ninth layer, and the circuit current should find the nearest grounding via (such as the grounding pin of elements such as resistance or capacitance). If you happen to have such a via nearby, you‘re really lucky. If there is no such close via available, the inductance will increase, the capacitance will decrease, and the EMI will increase. When the signal line must leave the current pair of wiring layers to other wiring layers through vias, grounding vias should be placed near the vias, so that the loop signal can return to the appropriate grounding layer smoothly. For the layered combination of layer 4 and layer 7, the signal loop will return from the power layer or ground layer (i.e. layer 5 or layer 6), because the capacitive coupling between the power layer and ground layer is good and the signal is easy to transmit.
Design of multi power layer
If two power layers of the same voltage source need to output large current, the circuit board shall be arranged into two groups of power layers and grounding layers. In this case, an insulating layer is placed between each pair of power layers and the grounding layer. In this way, we can get two pairs of power busbars with equal impedance. If the stack of power layers causes unequal impedance, the shunt will be uneven, the transient voltage will be much larger, and the EMI will increase sharply.
If there are multiple power supply voltages with different values on the circuit board, multiple power supply layers are required accordingly. Remember to create their own paired power supply layers and grounding layers for different power supplies. In the above two cases, when determining the position of the paired power layer and ground layer on the circuit board, remember the manufacturer‘s requirements for the balance structure.
In conclusion, since most of the circuit boards designed by engineers are traditional printed circuit boards with a thickness of 62mil and without blind holes or buried holes, the discussion of circuit board layering and stacking in this paper is limited to this. For circuit boards with too large thickness difference, the layering scheme recommended in this paper may not be ideal. In addition, the processing process of circuit boards with blind holes or buried holes is different, and the layering method in this paper is not applicable.
In the circuit board design, the thickness, via process and the number of layers of the circuit board are not the key to solve the problem. Excellent layered stacking is the key to ensure the bypass and decoupling of the power bus, minimize the transient voltage on the power layer or grounding layer, and shield the signal and the electromagnetic field of the power supply. Ideally, there should be an insulating isolation layer between the signal wiring layer and its circuit grounding layer, and the smaller the paired layer spacing (or more than one pair) should be, the better. According to these basic concepts and principles, we can design a circuit board that can always meet the design requirements. Now, the rise time of IC has been very short and will be shorter. The technology discussed in this paper is essential to solve the problem of EMI shielding.
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