Using dynamic voltage and frequency regulation to save system battery power requirements
Time:2023-11-27
Views:429
The energy consumed by mobile devices is a combination of switch energy and leakage energy. When switch energy dominates, reducing the power supply voltage level can effectively reduce total power consumption, as switch energy is proportional to the square of the power supply voltage.
Dynamic Voltage and Frequency Regulation (DVFS) can control the power supply voltage according to the operating frequency requirements, which is particularly effective for this purpose.
working frequency
In Figure 1 below, the solid black curve shows the dependence of energy consumption on operating frequency under DVFS. Here, the working frequency monotonically decreases with the decrease of power supply voltage.
When the operating frequency is higher than the energy point (MEP) of the power supply voltage (Vopt), the energy consumption decreases as the operating frequency decreases. However, when the operating frequency is lower than the operating frequency of MEP, energy consumption will increase as the operating frequency decreases.
When the power supply voltage approaches the threshold voltage of the LSI transistor, even small changes can cause significant changes in the operating frequency. In this case, the increase in leakage energy caused by an increase in working time will exceed any decrease in switch energy caused by a decrease in power supply voltage, resulting in an increase in total energy.
In this situation, relying solely on DVFS is not enough to reduce energy consumption. However, the proposed technique of combining DVFS with power gating (a technique to reduce leakage, where the power switch inserted between the power supply and the target circuit is turned off during idle time of the target circuit) has been proven to be more effective.
By combining DVFS and power gating, when the required frequency is lower than the frequency of MEP, the target circuit operates under Vopt and reduces leakage energy through power gating during idle time.
Although higher power supply voltage can lead to an increase in switch energy, the total energy is reduced more than the individual DVFS due to the decrease in leakage energy (see the red solid line in Figure 1 below, which also shows the block diagram of this scheme).
Figure 1: The solid black curve displays the relationship between energy consumption and operating frequency under DVFS.
The MEP monitor determines the Vopt used to reduce energy consumption, the delay monitor determines the required power supply voltage value to meet frequency requirements, and outputs a control signal to the regulator. The regulator responds by providing appropriate voltage to the target circuit.
When the determined power supply voltage is lower than Vopt, the MEP monitor disables the control signal and maintains the power supply voltage at Vopt. When the target circuit operates in Vopt, the MEP monitor also enables the power gate controller to control the power switch to reduce energy leakage during idle time. The MEP monitor controls the entire system to maximize operational energy and is a key component of this solution.
Although energy reduction largely depends on the accuracy of determining Vopt, the accuracy here is not easy, as Vopt largely depends on leakage current, which in turn depends on temperature, power supply voltage, and other factors. Many different methods have been proposed to address this issue.
Traditional and New
One method is to determine the Vopt based on the actual energy consumption measurement of the target circuit at different power supply voltage levels, and select the voltage with lower energy consumption. Due to the target circuit being used as an energy monitor, this scheme has a high degree of accuracy compared to MEP, but circuit operations must be paused during monitor operation.
Another traditional method is to use theoretical equations. For example, one approach is based on the fact that delta Earl/delta VDD=0 at MEP. In this method, Vopt is represented as equation 2.
Unfortunately, this method does not seem suitable for circuit implementation as it includes a parameter n, which has a non-linear dependence on the power supply voltage. NEC has designed a new method for determining Vopt, which consists of simple components and is suitable for circuit implementation.
Compared to previous methods, this new technology allows for simultaneous monitoring and circuit operations, and has been proven to be feasible. It is based on the fact that deltaEarth VDD=0 at MEP, where Earth is represented by formula 1 in Figure 1 above.
Please note that the differential of the (IL1T1-IL2T2)/Delta V is replaced by delta ILT)/delta VDD equation. Then formula 3 can be approximately derived, where Delta V is much smaller than VDD. IL1 and T1 are the leakage current and critical path delay at VDD, respectively, while IL2 and T2 are the leakage current and critical path delay at VDD Delta V. Due to the fact that both leakage current and critical path delay can be measured by a monitor, formula 3 is applicable to circuit implementation.
According to formula 3, we can determine Vopt as follows: its right side is equal to the voltage of the capacitor, which is initially charged to VDD, then charged for an additional T1 time with IL1, and discharged for T2 time with IL2. The capacitance of the capacitor is the product of the switching capacitance of the target circuit and the switching activity. For a given VDD, if the voltage of the capacitor is equal to VDD Delta V, then the VDD will be the voltage that reduces energy consumption.
Figure 2: The recommended voltage determiner and measurement results are shown
Circuit implementation
Figure 2 above shows the circuit used to determine Vopt. This is a very simple circuit consisting of a variable capacitor with a capacitance of alpha x C0; Two leakage current generators, each containing a replica of the target circuit; Two pulse generators, each containing a replica of the critical path of the target circuit; A comparator; And three switches. IL1 and IL2 flow out or into two leakage current generators respectively.
SW1, SW2, and SW3 are opened for initial charging, additional charging, and discharging of the capacitor, respectively. In order to turn on SW2 and SW3, the pulse generator generates signals with pulse widths of T1 and T2, respectively.
A test chip was manufactured using 90nm CMOS technology to evaluate the effectiveness of the circuit and the combination of DVFS and power gating. The target circuit is a 101 stage ring oscillator consisting of two input NAND gates with FO=4.
Figure 2 shows the dependence of the energy of the target circuit on the power supply voltage, as well as the points determined by the determiner circuit, where Delta V=20mV. The curve represents three temperatures (25 ℃, 75 ℃, and 125 ℃) under the condition of 0.1 switch activity.
This circuit can accurately determine the actual voltage value of MEP within 50mV under all conditions. Figure 2 also shows that at 125 ° C and Vopt=0.67V, using a 40MHz power gated Vopt operation can achieve a 52.8% reduction in energy consumption, which is higher than using only 5MHz DVFS.
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